The present invention relates to a semiconductor device functioning as a CMOS device having an NMOSFET and a PMOSFET.
A CMOS device having an NMOSFET and a PMOSFET on the same semiconductor substrate has conventionally been used very frequently as a device constituting a memory or a logic integrated circuit. Generally, a P well and an N well are formed in a region in the vicinity of the surface of a semiconductor substrate and NMOSFET and PMOSFET are respectively formed in the P well and N well. In particular, a so-called retrograde well, in which the peak of impurity concentration is formed deep inside of the semiconductor substrate by ion implantation, is often used recently.
Hereinafter, a retrograde well forming technology as set forth in NIKKEI MICRODEVICES, 1991, December, pp. 110-117 will be described.
FIGS. 11(a) to 11(c) are cross-sectional views illustrating the conventional process steps for producing so-called twin retrograde wells. In FIGS. 11(a) to 11(c), a P-well is to be formed in an NMOSFET forming region Rn and an N-well is to be formed in a PMOSFET forming region Rp.
In the step shown in FIG. 11(a), LOCOS layers 102 for defining the NMOSFET forming region Rn and the PMOSFET forming region Rp are formed on a Si substrate 101. Thereafter, an oxidation process is performed to form a protective oxide layer 125 on the surface of the Si substrate 101. A first resist layer Pr101, which is opened only above the NMOSFET forming region Rn, is also formed. By using the first resist layer Pr101 as a mask, B+ ions are implanted into the NMOSFET forming region Rn for forming a P well 103. By using the first resist layer Pr101 as a mask, B+ ions are also implanted three times for forming an NMOSFET threshold control layer 130, a punch-through stopper 131 and a channel stopper 132. The ion implantation is performed three times while varying implantation energy and implantation amount.
In a step shown in FIG. 11(b), the first resist layer Pr101 is removed, and then a second resist layer Pr102, which is opened above the PMOSFET forming region Rp, is formed. By using the second resist layer Pr102 as a mask, P+ ions are implanted for forming an N well 104. By using the second resist layer Pr102 as a mask, B+ ions are further implanted three times for forming a threshold control layer 133, a punch-through stopper 134 and a channel stopper 135.
In a step shown in FIG. 11(c), the second resist layer Pr102 is removed, and then the entire surface of the Si substrate 101 is etched to remove the protective oxide layer 125.
Although the illustration of the subsequent process steps is omitted, gate oxide layers, gate electrodes, source and drain regions and the like are formed in the NMOSFET forming region Rn and PMOSFET forming region Rp, thereby forming an NMOSFET and a PMOSFET in the respective regions.
However, the above-mentioned conventional method for producing a semiconductor device is disadvantageous in that the properties, such as reliability lifetime, of the gate oxide layers are deteriorated. This is because, when ions are implanted, not only an impurity for generating carriers (i.e., additive impurity), but also an impurity, which adversely affects the properties of the gate oxide layers (hereinafter, such a impurity will be referred to as a "foreign impurity") are introduced into the vicinity of the surface of the oxide layers.
More specifically, when additive impurity ions are implanted by using the first resist layer Pr101 as a mask in the step shown in FIG. 11(a), the foreign impurity is simultaneously implanted into the vicinity of the surface of the protective oxide layer 125 and into the vicinity of the surface of the LOCOS layers 102.
By the time the process step shown in FIG. 11(c) is performed, the foreign impurity, which has been introduced into the protective oxide layer 125 and the LOCOS layers 102 in the step shown in FIG. 11(a), is exposed to high temperature when the first and the second photoresist layers Pr101 and Pr102 are removed. Accordingly, the foreign impurity possibly diffuses inward from the surface of the LOCOS layers 102 or is combined with other impurity to be a compound which cannot be removed even if the protective oxide layer 125 is etched. As a result, when the step shown in FIG. 11(c) is finished, the foreign impurity is residual at any site on the substrate.
If gate oxide layers are formed on the Si substrate 101 by thermal oxidation or the like after the step shown in FIG. 11(c) has been performed, the residual foreign impurity might diffuse or scatter so as to enter the gate oxide layers.
As a result, some defect, such as an impurity level, is caused in the gate oxide layers, thereby presumably deteriorating the properties, such as reliability lifetime, of the gate oxide layers. It has not been researched sufficiently what chemical substance is the foreign impurity and how the foreign impurity is introduced into the gate oxide layers. However, it is already known that such a phenomenon is found remarkable if ion implantation is performed with high energy.
Such a foreign impurity can be removed to a certain degree by means of baking or the like. However, if such a heat treatment is additionally performed, then the number of process steps is undesirably increased. In addition, other problems possibly arise. For example, since the additive impurity is diffused because of the heat applied, a desired impurity profile may not be obtained in some cases.
The above-mentioned deterioration in properties, such as reliability lifetime, of the gate oxide layers caused by the foreign impurity is brought about not only in the step of forming a retrograde well, but also in the steps of forming NMOSFETs and PMOSFETs in the P well and N well which have been formed by diffusion, for example. This is because, in the conventional process generally employed, ion implantation is often performed at high energy in each of the P well and N well with the protective oxide layer deposited, in order to form not only a threshold control layer, but also a punch-through stopper or a channel stopper.
Of the CMOS devices, in a semiconductor device having a thick-layer MOSFET having a thick gate oxide layer for a high voltage (high gate breakdown voltage) and a thin-layer MOSFET having a thin gate oxide layer for a low voltage (low gate breakdown voltage), in particular, if such a device is additionally subjected to a heat treatment such as baking, then the desired electric characteristics cannot be obtained. It is therefore difficult to suppress the deterioration in reliability lifetime of the gate oxide layers owing to the foreign impurity. Also, when the gate oxide layer of the thick-layer MOSFET is used as a protective layer for forming the punch-through stopper of the thin-layer MOSFET, the oxide layer cannot be etched over the entire surface of the wafer. Thus, it is difficult to remove the foreign impurity.